In British patent application number 0226732.6 an architecture is described which supports demodulation of a wide range of analogue and digital signal formats. One key element of that architecture is a single instruction multiple data (SIMD) programmable processor which is closely coupled to a memory unit which provides access to multiple data words in each clock cycle. In one embodiment of the invention, it is necessary to read or write four independent data values in each clock cycle.
In U.S. Pat. No. 5,669,010: “cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units”, a number of SIMD processor arrangements are described which consist of a number of arithmetic units and multi-port memories. This patent does not describe how to build a suitable multi-port memory using single-ported Memories.
In U.S. Pat. No. 6,189,073: “Method of emulating dual-port memory device using an internally-cached static random access memory architecture”, a hierarchical caching arrangement of memories is described which gives dual-port access to a large single-port memory. This arrangement is not suitable for an SIMD processor such as the one described in British patent application number 0226732.6.
In U.S. Pat. No. 6,434,674: “Multi-port memory architecture with direct data flow”, an arrangement is described which gives multi-port access to a large single-port memory which has wider data bus width and faster cycle time than the memory ports. This arrangement is not suitable for an SIMD processor such as the one described in British patent application number 0226732.6.
In U.S. Pat. No. 6,282,505: “Multi-port memory and a data processor accessing the same”, an arrangement is described which gives dual-port access to two independent single-port memories by allocating each of the two input ports to each of the two memories on successive clock cycles. This arrangement is not suitable for an SIMD processor such as the one described in British patent application number 0226732.6.
In U.S. Pat. No. 6,212,607: “Multi-ported memory architecture using single-ported RAM”, an arrangement is described which gives multi-port access to a number of independent single-port memories using a combination of bus grant signals, interrupts and mailboxes. This arrangement allows multiple processing devices to share a common memory area, but the arrangement is not suitable for a SIMD processor such as the one described in British patent application number 0226732.6.
The preferred embodiment of the invention described here provides an efficient structure for implementation of the multi-port memory required in a processor of the type described in British patent application number 0226732.6 using a plurality of single-port memories.
A SIMD processor such as the one described in British patent application number 0226732.6 requires a multi-port memory providing N independent accesses to memory in one clock cycle. A conventional multi-port semiconductor memory allowing N simultaneous independent accesses per clock cycle is in general larger than N independent single-port semiconductor memories with the same total storage capacity as the multi-port memory. The larger size is due to the extra circuitry required to provide multiple independent accesses to each memory cell. In a semiconductor chip which requires a multi-port memory it is desirable to minimise the chip area occupied by the memory. An arrangement that provides multi-port access to a plurality of single-port memories can provide a significant reduction in chip area for a given memory storage capacity.